A 65-nm CMOS DAC Based on a Differentiating Arbitrary Waveform Generator Architecture for 5G Handset Transmitter

Abstract

The data rate expected for the forthcoming 5G standard induces stringent constraints for handset transceivers. Wideband carrier aggregation will be handled with flexible and low-power architectures implemented in low-cost technologies. An architecture of a wideband signal generator intended to target sub-6-GHz 5G transmission requirements is presented. The architecture is based on a differential pulse code modulation coding scheme and a custom integrating DAC named the Riemann pump. It performs a 9-dB improvement of the signal-to-noise ratio per doubling of the oversampling ratio while ensuring a flat quantization noise floor over the whole multigigahertz conversion band. Its inherent ability to generate synchronous signals allows us to address carrier aggregation purposes; the generation of 10 synchronized 64-QAM modulated signals between 1.8 and 3.6 GHz is simulated. Postlayout simulations of the Riemann pump implemented in 65-nm CMOS technology fit the exposed theoretical features with a submilliwatt-level power consumption.