A 72K CMOS Channelless Gate Array with Embedded 1Mbit Dynamic RAM

Abstract

A lMbit DRAM is embedded in 72K raw gates channelless gate array with 1 .Opm HC2MOS twin well technology. The DRAM design is optimized for embedding, such as the adoption of no substrate bias design and p-well protected nchannel memory cells. The typical delay time of the gate array is 0.4ns and the worst case access time of the DRAM is 60ns.