1988 · 16 citations · 1 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignEmbedded Memory BlocksMemory DevicesMemory Hierarchy DesignMemory Subsystem DesignTiming AnalysisDynamic Random-access Memory DesignGate Array DesignMemory Array ArchitectureMemory Circuit DesignNon-volatile Memory DesignOn-chip Memory Design
A lMbit DRAM is embedded in 72K raw gates channelless gate array with 1 .Opm HC2MOS twin well technology. The DRAM design is optimized for embedding, such as the adoption of no substrate bias design and p-well protected nchannel memory cells. The typical delay time of the gate array is 0.4ns and the worst case access time of the DRAM is 60ns.
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Transparent-refresh DRAM (TReD) using dual-port DRAM cell
T. Sakurai, K. Nogami, K. Sawada et al. · 2003 · 12 citations