A New Mixed Gate Diffusion Input Full Adder Topology for High Speed Low Power Digital Circuits

Abstract

This paper mainly presents Mixed Gate Diffusion Input Full Adder based on static CMOS inverter topology. In this proposed mixed Full Adder topology, GDI Full adders are followed by inverters in the long Full Adder chain to improve the performances as compared to conventional single topology Full adder chain. For any circuits reducing the speed and power dissipation are the important constraints. By changing the number of full adders between two consecutive inverters the delay, the dynamic and leakage power dissipation can be optimized. Delay and power has been evaluated by HSPICE simulation using TSMC 0.35µm and 0.18µm CMOS technologies considering minimum power design. The simulation results reveal better delay and power performance of proposed mixed full adder topology as compared to existing mixed Full Adder topologies at both 0.35µm and 0.18µm CMOS technologies.