Generation of Multigrid-based Numerical Solvers for FPGA Accelerators

Abstract

Not only in the field of High-Performance Computing (HPC), Field Programmable Gate Arrays (FPGAs) are a soaringly popular accelerator technology. However, they increase the heterogeneity of clusters, which might be equipped already today with accelerators, such as GPUs. This results in having to combine expertise from different fields, e. g., math-ematical, algorithmic and technical experts are needed to create numerical solvers for such systems. To bridge this programmability gap, Domain-Specific Languages (DSLs) are a popular choice to generate low-level implementations from an abstract algorithm description. In this work, we demonstrate the generation of implementations of numerical solvers based on the multigrid method for FPGAs from the same codebase that is also used to generate code for CPUs using a hybrid parallelization of MPI and OpenMP. Our ap-proach yields in a hardware design that can compute up to 12 V-cycles per second with an input grid size of 4096×4096 on a mid-range FPGA, beating vectorized, single-threaded execution on an Intel i7 by a factor of almost three. 1.