Minimization of Floorplanning Area and Wire Length Interconnection Using Particle Swarm Optimization

Abstract

Abstract — Floorplanning is an essential design step for hierarchical building module design methodology. Floorplanning provides early feedback that evaluates architectural decisions, estimates chip area, estimates delay and congestion caused by wiring. As technology advances, design complexity is increasing and the circuit size is getting larger. To cope with the increasing design complexity, hierarchical design and Intellectual Property modules are widely used. This makes floorplanning much more critical to the quality of a Very Large Scale Integration (VLSI) design. For many years, floorplanning is a critical step, as it sets up the ground work for a layout. However, it is computationally quite hard. The process of determining block shapes and positions with area minimization objective and aspect ratio requirement is referred to as floorplanning. Common strategy for blocks floorplanning is to determine in the first phase and then the relative location of the blocks to each other based on connection-cost criteria. In the second step, block sizing is performed with the goal of minimizing the overall chip area and the location of each block is finalized. From the computational point of view, VLSI floorplanning is NP-hard. The solution space will increase exponentially with the growth of circuits scale, thus it is difficult to find the optimal solution by exploring the global solution space. To handle this complexity swarm based optimization method has opted in this proposed work. A generalize solution has developed to take care of area as well as interconnection wire length. To achieve this weighted objective function has defined. The advantages of PSO like simplicity in implementation, not depends upon the characteristics of objective function and better performance have given support to include it as a solution method.