Skew management of NBTI impacted gated clock trees

Abstract

NBTI (Negative Bias Temperature Instability) has emerged as the dominant failure mechanism for PMOS in nanometer IC designs. However, its impact on one of the most important components of modern IC design - the clock tree - has not been researched enough. Clock gating impacts the extent of NBTI induced VTH degradation of clock buffers leading to clock skew violation. Our work proposes a practical design-time technique of selecting NAND or NOR gate as output stage of integrated clock gating (ICG) cells with the objective of minimizing NBTI induced clock skew. This selection intelligently modulates the signal probability and delay equation of clock signal paths with no extra hardware penalty. We formulate the skew minimization problem as an integer linear program (ILP). Experimental results demonstrate the effectiveness of our method as the NBTI induced clock skew is reduced by more than 74% compared to traditional method.