IEEE Journal of Solid-State Circuits · 1981 · 25 citations · 9 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignLow-power Digital Circuit DesignMixed-signal IntegrationPower ManagementCharge DistributionCmos Analog Circuit DesignCmos Analog Integrated CircuitsLow-power Cmos DesignSwitched-capacitor Circuit DesignSwitched-capacitor CircuitsSwitched-capacitor Filters
A complete PCM codec using charge redistribution and switched-capacitor techniques will be described. The device is implemented in a two-level polysilicon CMOS technology using 23.4 mm/SUP 2/ of active area. It features all the required transmission filters needed for telephony, two on-chip voltage references, TTL compatible digital interfaces, and low-power dissipation. The architecture of the chip allows asynchronous operation, a variable PCM data rate from 100 kbit/s to 4.096 Mbit/s, /spl mu//A law operation via pin selection, and gain selection at either of two levels in each direction.
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