IEEE Journal of Solid-State Circuits · 2008 · 16 citations · 1 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsSensorsAnalog Integrated CircuitsClock ManagementDigital Integrated CircuitsDigital Signal ProcessingLow-noise Circuit DesignMixed-signal Integrated Circuit DesignA-d ConversionAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital Converter DesignAnalog-to-digital ConvertersDigital Signal Processing Block ArchitecturePipeline ArchitecturePipelined Digital Circuits
In this paper, a novel 10-bit A/D converter based on a pipeline-like architecture specific for low-noise, self-triggered sensors, (e.g., X-rays and 7-rays spectrometry) is presented. The main innovative feature of the proposed A/D structure is the concept that, for a sampled input signal, a pipeline ADC may behave as a combinatorial logic and may operate without any timing signal (clock). The conversion is obtained asynchronously propagating the partial conversions and the residues through the various stages. This concept is validated by means of a prototype ADC fabricated in a standard 0.35 mum CMOS technology. The active area is 2.24 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and it provides a conversion in 2.5 mus (i.e., it can operate with a 400 kS/s data rate) featuring an ENOB equal to 8.91.
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Analog Design for CMOS VLSI Systems
Mile Stojčev · Microelectronics Journal · 2003 · 78 citations
Engineering, Computer Engineering, Electrical Engineering +14