An MPSoC Performance Estimation Framework Using Transaction Level Modeling

Abstract

To use the tremendous hardware resources available in next generation multiprocessor systems-on-chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) methods are needed to evaluate the different design alternatives. In this paper, we present a framework that makes fast simulation and performance evaluation of MPSoC possible early in the design flow, thus reducing the time-to-market. In this framework and within the transaction level modeling (TLM) approach, we present a new definition of the timed programmer's view (PVT) level by introducing two complementary modeling sublevels. The first one, PVT transaction accurate (PVT-TA), offers a high simulation speedup factor over the cycle accurate bit accurate (CABA) level modeling. The second one, PVT event accurate (PVT-EA), provides a better accuracy with a still acceptable speedup factor. An MPSoC platform has been developed using these two sublevels including performance estimation models. Simulation results show that the combination of these two sublevels gives a high simulation speedup factor of up to 18 with a negligible performance estimation error margin.