Analog circuits in ultra-deep-submicron CMOS

TLDR

Ultra‑deep‑submicron CMOS introduces challenges such as nonlinear output conductance, reduced voltage gain, gate‑leakage mismatch, limited matching improvement with area, and supply‑voltage drops that constrain analog design. The paper proposes composite transistors to address these supply‑voltage and matching challenges in UDSM analog circuits. The authors use a mix of thin‑ and thick‑oxide transistors to raise critical part supply voltages, enabling the composite transistor solution. Measured data yield practical rules of thumb for managing the identified UDSM analog design issues.

Abstract

Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena.