A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS

Abstract

An asynchronous 6 bit 1 GS/s ADC is achieved by time interleaving two ADCs based on binary successive approximation algorithm (SA) using a capacitive ladder. The semi-close loop asynchronous technique eliminates the high internal clocks and significantly speeds up the SA algorithm. One bit redundancy is implemented to compensate the process variation of parasitic and the MOM capacitance. Fabricated in 65 nm CMOS with an active area of 0.11 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , it achieves a peak SNDR of 31.5 dB at 1 GS/s sampling rate and has a power consumption of 6.7 mW for the analog and digital processing.