Publication | Closed Access
A 71dB dynamic range third-order ΔΣ TDC using charge-pump
18
Citations
4
References
2012
Year
Unknown Venue
Low-power ElectronicsElectrical EngineeringEngineeringAnalog-to-digital ConverterDedicated Feedback DacData ConverterThird-order δς TdcAnalog DesignDynamic Range Third-orderMixed-signal Integrated CircuitDigital Circuit DesignPower ElectronicsPrototype Tdc
A high resolution time-to-digital converter (TDC) architecture is proposed. The architecture combines the principles of noise-shaping quantization and charge-pump to build a third-order ΔΣ TDC with a dedicated feedback DAC. Fabricated in a 0.13μm CMOS process, the prototype TDC achieves better than 71dB DR and 67dB SNDR in 2.81MHz signal bandwidth (OSR=16) and consumes 2.58mW.
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