Text searching on Splash 2

Abstract

The paper proposes a flexible, reprogrammable hardware solution to the acceleration of text-based keyword search problems. In these problems, a stream of input text is checked against a known list of keywords (a dictionary) for occurrences of those keywords in the text. The authors' solution employs an attached processor called Splash 2, which exploits the speed and reconfigurability of field programmable gate array technology. The Splash 2 system was designed and built at the SRC for a wide variety of applications. A Splash 2 system is comprised of an interface board to a Sun Sparc-2 host and up to 16 Splash boards, each of which contains 16 Xilinx 4010 FPGAs interconnected in a linear array and also through a 16-way full crossbar switch. Each Xilinx chip is coupled with a 4 Mbit static RAM through a dedicated interface. The text searching program implemented on a one-board Splash 2 system is capable of processing text at an estimated rate of 50 million characters per second.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>