2011 · 57 citations · 7 references
EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignWireless CommunicationsCmos Circuit DesignLow-noise Circuit DesignLow-power Digital Circuit DesignReceiver SystemsSensor NetworksWireless Sensor NetworksLow-power Amplifier DesignLow-power Cmos DesignLow-power Wireless CommunicationPower ConsumptionReceiver DesignReceiver SensitivitySensor NodesUltra-low-power Cmos
This paper presents a complete ultra-low power receiver with direct down conversion architecture. It is designed as Wake-up Receiver for wireless sensor nodes. The 130nm CMOS chip includes envelope detector, low noise baseband amplifier, PGA, mixed-signal correlation unit and auxiliaries for stand-alone operation. At 868MHz, a receiver sensitivity of -71dBm is achieved with total power consumption of 2.4μW at 1.0V supply by means of baseband correlation over 7ms with 64 bit pattern, 99% detection probability and a false wake-up rate of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> /s.
7
A 2GHz 52¿W Wake-Up Receiver with -72dBm Sensitivity Using Uncertain-IF Architecture
Nathan Pletcher, Simone Gambini, Jan M. Rabaey · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 2008 · 175 citations
Engineering, Computer Engineering, Electrical Engineering +17