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A 2.4µW Wake-up Receiver for wireless sensor nodes with −71dBm sensitivity
56
Citations
7
References
2011
Year
Unknown Venue
Low-power ElectronicsConversion ArchitectureElectrical EngineeringCmos ChipEngineeringRadio FrequencySensorsMixed-signal Integrated CircuitComputer EngineeringW Wake-up ReceiverWireless Sensor NodesSensor InterfaceSignal ProcessingEnvelope DetectorRf Subsystem
This paper presents a complete ultra-low power receiver with direct down conversion architecture. It is designed as Wake-up Receiver for wireless sensor nodes. The 130nm CMOS chip includes envelope detector, low noise baseband amplifier, PGA, mixed-signal correlation unit and auxiliaries for stand-alone operation. At 868MHz, a receiver sensitivity of -71dBm is achieved with total power consumption of 2.4μW at 1.0V supply by means of baseband correlation over 7ms with 64 bit pattern, 99% detection probability and a false wake-up rate of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> /s.
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