On design and implementation of a decimation filter for multistandard wireless transceivers

Abstract

In this work, we deal with the design and implementation of a decimation filter to be used in wideband radio-frequency receiver. The paper outlines architecture considerations for multistandard wireless transceivers. Also, it describes the design steps and the tradeoffs concerning the hardware implementation. GSM and DECT standards specifications are met by the proposed filtering cascade structure. The filter processes six-bit data stream input from a fourth-order sigma-delta modulator and has been prototyped in a field-programmable gate array device.