Publication | Closed Access
A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System
519
Citations
21
References
2010
Year
Medical ElectronicsEngineeringFeature ExtractionNeurophysiological BiomarkersElectroencephalographyMedical InstrumentationBiomedical Signal AnalysisSocial SciencesBiosignal ProcessingCognitive ElectrophysiologyNeurologyElectrical EngineeringComputer EngineeringNeurological MonitoringNeuroimagingEpilepsy PatientsSignal ProcessingNeural InterfaceBrain-computer InterfaceBiomedical SensorsNeuroengineeringNeurophysiologyEeg Signal ProcessingBioelectronicsBiomedical InstrumentationElectrophysiologyNeuroscienceBrain ElectrophysiologyBraincomputer InterfaceEeg Acquisition
The system is designed for chronic seizure monitoring, where a single‑channel SoC can be combined with up to 18 channels to capture EEG for epilepsy patients. The paper introduces a low‑power SoC that simultaneously acquires EEG and extracts features for continuous seizure‑onset detection in epilepsy patients. The SoC integrates a chopper‑stabilized instrumentation amplifier, a power‑gated ADC, and a low‑power feature‑extraction processor that streams 0.5‑Hz feature vectors to a central device running a machine‑learning classifier. Integrating sensing and local processing reduces system power by 14× by cutting wireless data transmission, and the one‑channel SoC consumes only 9 µJ per feature vector from a 1 V supply.
This paper presents a low-power SoC that performs EEG acquisition and feature extraction required for continuous detection of seizure onset in epilepsy patients. The SoC corresponds to one EEG channel, and, depending on the patient, up to 18 channels may be worn to detect seizures as part of a chronic treatment system. The SoC integrates an instrumentation amplifier, ADC, and digital processor that streams features-vectors to a central device where seizure detection is performed via a machine-learning classifier. The instrumentation-amplifier uses chopper-stabilization in a topology that achieves high input-impedance and rejects large electrode-offsets while operating at 1 V; the ADC employs power-gating for low energy-per-conversion while using static-biasing for comparator precision; the EEG feature extraction processor employs low-power hardware whose parameters are determined through validation via patient data. The integration of sensing and local processing lowers system power by 14× by reducing the rate of wireless EEG data transmission. Feature vectors are derived at a rate of 0.5 Hz, and the complete one-channel SoC operates from a 1 V supply, consuming 9 ¿ J per feature vector.
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