The performance analysis of an input access scheme in a high-speed packet switch

Abstract

The performance analysis of an input access scheme in a high-speed packet switch for broadband ISDN is presented. In this switch, each input maintains a separate queue for each of the outputs, thus there are n/sup 2/ input queues in a (n*n) switch. Using synchronous operation, at most one packet per input and output will be transferred in any slot. The choice of the packets is done in a manner to maximize the throughput of the switch. Comparison of simulations with analytically derived upper and lower bounds show close to optimal throughput. The mean packet delay is also derived and its variance is bounded. This input access scheme may be implemented using neural networks.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>