Harnessing FPGAs for computer architecture education

Abstract

Computer architecture and design is often taught by having students use software to design and simulate individual pieces of a computer processor. We are working on a method that will take this classwork beyond software simulation into actual hardware implementation. Students will be able to design, implement, and run a single-cycle MIPS processor on an FPGA. This paper presents the first steps in this work: an FPGA-optimized MIPS processor, a debugging tool which provides complete control and observability of the processor, and the reduction of the MIPS instruction set into eight instructions that will be used by the processor. Keywords FPGAs, FPGA-optimized CPU, Reduced MIPS Instruction Set, Debugging Tool, Communication Protocol 1.