A multi-channel ADC for use in the PHENIX detector

TLDR

The paper discusses circuit topologies and ASIC layout specifics, such as power consumption, maximum clock speed, INL, and DNL. A custom 8‑channel CMOS ADC ASIC was fabricated in a 1.2 µm process using a Wilkinson architecture with differential positive‑ECL input and selectable 11‑ or 12‑bit conversions, designed for multi‑channel use in PHENIX subsystems. The ADC achieved 11‑bit accuracy.

Abstract

A custom CMOS analog to digital converter was designed and a prototype 8-channel ADC ASIC was fabricated in a 1.2 /spl mu/m process. The circuit uses a Wilkinson-type architecture which is suitable for use in multi-channel applications such as the PHENIX detector. The ADC design features include a differential positive-ECL input for the high speed clock and selectable control for 11 or 12-bit conversions making it suitable for use in multiple PHENIX subsystems. Circuit topologies and ASIC layout specifics, including power consumption, maximum clock speed, INL, and DNL are discussed. The ADC performed to 11-bit accuracy.