Delay uncertainty due to on-chip simultaneous switching noise in high performance CMOS integrated circuits

Abstract

On-chip parasitic inductance inherent to the power supply rails has become significant in high speed digital circuits. Therefore, current surges result in voltage fluctuations within the power distribution networks, creating delay uncertainty. On-chip simultaneous switching noise should therefore be considered when estimating the propagation delay of a CMOS logic gate in high speed synchronous CMOS integrated circuits. Analytical expressions characterizing the on-chip simultaneous switching noise voltage and the output voltage waveform of a CMOS logic gate driving both a capacitive and a resistive-capacitive load are presented. The waveform of the output voltage signal based on the analytical expressions is quite close to SPICE. The estimated propagation delay is within 5% as compared to SPICE while the average improvement in accuracy can reach 10% as compared to a delay estimated without considering on-chip simultaneous switching noise. The analytical expressions presented provide an accurate timing model for non-negligible on-chip simultaneous switching noise in high speed synchronous CMOS integrated circuits.