The STC104 Packet Routing Chip

Abstract

High‐performance parallel systems demand a high‐performance interconnect so that their component parts can exchange data and synchronise efficiently. The interconnect must be cheap, and must also scale well in both performance and cost relative to the system size. In this paper we describe the rationale, architecture and operation of the STC104, the first commercially available, general‐purpose interconnect chip. The serial protocols used by the device are described, followed by an overview of the microarchitecture, The operation of the fundamental block is outlined, including the response to error conditions. Chip‐wide design issues and design methodology are discussed, and finally various aspects of performance are calculated.