Multiplierless approximate 4‐point DCT VLSI architectures for transform block coding

Abstract

Two multiplierless algorithms are proposed for 4 × 4 approximate‐discrete cosine transform (DCT) for transform coding in digital video. Computational architectures for one‐dimensional (1D)/2D realisations are implemented using Xilinx field programmable gate array devices. CMOS synthesis at the 45 nm node indicates real‐time operation at 1 GHz yielding 4 × 4 block rates of 125 MHz at < 120 mW of dynamic power consumption.