Performance Evaluation and Synthesis of Multiplier Used in FFT Operation Using Conventional and Vedic Algorithms

Abstract

New telecommunication systems are based more than ever before on digital signal processing. High speed digital telecommunication systems such as OFDM and DSL need real-time high-speed computation of the Fast Fourier Transform. Thus there is a need of innovative algorithms to improve the speed. In this paper, we propose vedic algorithm for the implementation of multipliers to be used in the FFT. Vedic mathematics (VM) comes with the simplest and effective algorithm for solving any typical engineering problem standing on the pillars of the “Vedic” principles. The conventional multiplication method requires more time & area on silicon than vedic algorithms. More importantly processing speed increases with the bit length. This will help ultimately to speed up the signal processing task, as it is well known that the multiplier is the basic building block of FFT. The VM has been synthesized for the target device 5vlx30ff324-3.