Analog routing for manufacturability

Abstract

The goal of a performance-driven routing tool is to route an analog circuit such that the performance degradation caused by layout parasitics remains within the specification margins imposed by the designer. For a given set of circuit specifications, several valid routing solutions can be found. In this paper, we propose an algorithm that selects the solution that additionally maximizes the yield and the testability of the resulting layout. Initially, the circuit is routed with a cost function designed to enforce all performance constraints. After all nets have been routed, the layout parasitics are extracted and the performance of the circuit is verified. In a second phase, nets are ripped up and rerouted to optimize the yield and the testability of the layout. During this process, care is taken not to introduce performance constraint violations. An industrial example, is presented to demonstrate the effectiveness of the approach.