Shift-Or Circuit for Efficient Network Intrusion Detection Pattern Matching

Abstract

This paper introduces a novel FPGA-based signature match co-processor architecture serving as the core of a hardware-based network intrusion detection system (NIDS). The signature match co-processor architecture is based on the shift-or algorithm. The architecture is comprised of simple shift registers, or-gates, and ROMs where patterns are stored. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of NIDS systems