Investigation on the clamping voltage self-balancing of the three-level capacitor clamping inverter

Abstract

This paper deals with the self-balancing quality of the clamping voltage in the three-level capacitor clamping inverter due to the spontaneous clamping capacitor current control loop in the circuit. Self-balancing quality of the three-level capacitor clamping inverter under sub-harmonic PWM modulation is analyzed in detail. The self-balancing mechanism in the multilevel capacitor clamping inverter (M>3) under sub-harmonic PWM modulation is also discussed. Test results regarding the self-balancing quality from a half-bridge three-level capacitor clamping inverter prototype under sub-harmonic PWM modulation is given.