Publication | Closed Access
The RAP: a ring array processor for layered network calculations
31
Citations
12
References
2002
Year
Unknown Venue
EngineeringNeural Networks (Machine Learning)Advanced ComputingHigh Performance Computer NetworkComputer ArchitectureNetwork AnalysisInterconnection Network ArchitectureHardware SystemsSpeech RecognitionArray ComputingHigh-performance ArchitectureComputing SystemsSystems EngineeringParallel ComputingPhysical LayerArray ProcessorComputer EngineeringComputer ScienceHardware AccelerationSpeech ProcessingParallel ProgrammingFast ImplementationRing Array Processor
The authors have designed and implemented a ring array processor, RAP, for fast implementation of layered neural network algorithms. The RAP is a multi-DSP system targeted at continuous speech recognition using connectionist algorithms. Four boards, each with four Texas Instruments, TMS 320C30 DSPs, serve as an array processor for a 68020-based host running a real-time operating system. The overall system is controlled from a Sun workstation via the Ethernet. Each board includes 16 MB of dynamic memory (expandable to 64 MB) and 1 MB of fast static RAM. Theoretical peak performance is 128 MFLOPS/board, and test runs with the first working board show a sustained throughput of roughly one-third to one-half of this for algorithms of interest. Software development is aided by a Sun workstation-based command interpreter, tools from the standard C environment and a library of matrix and vector routines.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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