Titan: Enabling large and complex benchmarks in academic CAD

TLDR

Benchmarks are essential for FPGA architecture and CAD research, yet most existing ones are small and simple, failing to reflect modern large‑scale heterogeneous designs. This paper introduces Titan, a hybrid CAD flow designed to provide large, complex benchmarks for academic FPGA research. Titan employs Altera’s Quartus II for HDL synthesis, converts the output to academic BLIF format, and uses the resulting Titan23 set of 23 large benchmarks to compare VPR and Quartus II performance on a detailed Stratix IV model. The comparison shows VPR is at least 2.7× slower, consumes 5.1× more memory, and uses 2.6× more wire than Quartus II, largely due to VPR’s emphasis on dense packing.

Abstract

Benchmarks play a key role in FPGA architecture and CAD research, enabling the quantitative comparison of tools and architectures. It is important that these benchmarks reflect modern designs which are large scale systems that make use of heterogeneous resources; however, most current FPGA benchmarks are both small and simple. In this paper we present Titan, a hybrid CAD flow that addresses these issues. The flow uses Altera's Quartus II FPGA CAD software to perform HDL synthesis and a conversion tool to translate the result into the academic BLIF format. Using this flow we created the Titan23 benchmark set, which consists of 23 large (90K-1.8M block) benchmark circuits covering a wide range of application domains. Using the Titan23 benchmarks and a detailed model of Altera's Stratix IV architecture we compared the performance and quality of VPR and Quartus II targeting the same architecture. We found that VPR is at least 2.7× slower, uses 5.1× more memory and 2.6× more wire compared to Quartus II. Finally, we identified that VPR's focus on achieving a dense packing is responsible for a large portion of the wire length gap.