Design of Highly Efficient Three-Stage Inverted Doherty Power Amplifier

Abstract

This letter reports the highly efficient three-stage inverted Doherty power amplifier (IDPA) using 30 W and 50 W Si LDMOSFETs. The characteristic impedances of the output combiner are derived to achieve high efficiency at a large back-off power (BOP). The output matching networks and offset lines of the carrier and peaking cells are used to modulate the load impedance. The transmission line in the input path of the carrier cell is inserted to adjust the delay among the carrier and peaking cells. The drain efficiency (DE) of 40.3% with a gain of 9 dB is achieved at output power of 42 dBm (8.5 dB BOP) and the DE above 40% is maintained in wide output range for a 2.14 GHz continuous wave signal. For a one-carrier WCDMA signal at an output power of 40 dBm (10.5 dB BOP), the DE of 35% with the gain of 9.2 dB is achieved.