MOVE: a framework for high-performance processor design

Abstract

CPU architectures allowing exploitation of instruct ion-level par­ allelism (pipelining, VllW, supersc alar) exhibit poor average hardware utilization and complex hardware organizations. We propose a different architecture with a less complex hardware or­ ganization and significantly better hardware utilization. This ar­ chitecture allows short cycle implementations, and is easily con­ figurable in functionality and scalable in performance. Besides being suitable for high-performance general-purpose computing, the architecture is particularly useful as framework for the (semi) automaJic generation of high-performance processo rsfor specific applications. The key feature of this architecture is the separation of data trans­ port and data operations. This separation yields a degree of auto­ nomicity for the different operational units which allows,for exam­ ple, diff erent units to implement different pipelining schemes. Fur­ thermore this separation allows the machine cycle to be reduced to the transport delay. The resulting programming model is quite unusual and provides scheduling possibilities unexploitable in the aforementioned architectures. We believe this architecture will be a favorable candidaJe for future powerful computing systems.