The digital silicon photomultiplier — Principle of operation and intrinsic detector performance

Abstract

We developed a fully digital implementation of the Silicon Photomultiplier. The sensor is based on a single photon avalanche photodiode (SPAD) integrated in a standard CMOS process. Photons are detected directly by sensing the voltage at the SPAD anode using a dedicated cell electronics block next to each diode. This block also contains active quenching and recharge circuits as well as a one bit memory for the selective inhibit of detector cells. A balanced trigger network is used to propagate the trigger signal from all cells to the integrated time-to-digital converter (TDC). Photons are detected and counted as digital signals, thus making the sensor less susceptible to temperature variations and electronic noise. The integration with CMOS logic has the added benefit of low power consumption and possible integration of data post-processing. In this paper, we discuss the sensor architecture and present first measurements of the technology demonstrator test chip.