A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a

Abstract

We propose an all-digital UWB transmitter architecture that exploits the low duty cycle of impulse-radio UWB to achieve ultra-low power consumption. The design supports the IEEE 802.15.4a standard and is demonstrated for its mandatory mode. A digitally controlled oscillator produces the RF carrier between 3 and 10 GHz. It is embedded in a phase-aligned frequency-locked loop that starts up in 2 ns and thus exploits the signal duty cycle that can be as low as 3%. A fully dynamic modulator shapes the BPSK symbols in discrete steps at the 499.2 MHz chip rate as required by the standard. The transmitter can operate in any 499.2 MHz band of the standard between 3.1 and 10 GHz, and the generated signal fulfills the emission spectral mask. The jitter accumulation over a burst is below 6 ps <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RMS</sub> , which is within specifications. The transmitter was realized in a 1 V 90 nm digital CMOS technology, and its power consumption drawn from a 1 V supply is from 0.65 mW at 3.1 GHz to 1.4 mW at 10 GHz for a 1 Mb/s data rate.