A novel built-in self-repair approach to VLSI memory yield enhancement

Abstract

The feasibility of implementing electronic neural networks as intelligent hardware for memory array repair is demonstrated. In particular, it is shown that the neural network control possesses a robust and degradable computing capability under various fault conditions. A yield analysis performed on 64K DRAMs shows that the yield can be improved from as low as 20% to near 99% owing to the self-repair design, with an overhead of no more than 7%. Simulation shows that the neural net algorithms are superior to the Repair Most algorithm.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>