A 1-GS/s 6-Bit Two-Channel Two-Step ADC in 0.13-$\mu$m CMOS

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> In this paper, a 6-bit 1-GS/s 49 mW two-channel two-step analog-to-digital converter (ADC) without calibration is implemented in 0.13-<formula formulatype="inline"> <tex Notation="TeX">$\mu{\hbox {m}}$</tex></formula> CMOS process. The proposed multiplying digital-to-analog converter (MDAC) processes the analog signal with two clock periods for one conversion: half for sampling, half for Coarse ADC (CADC) resolving, and one for residue amplification. A self-timing technique is used to prevent disturbance at the beginning of the residue amplification. The reduction of the MDAC output swing by enhancing the accuracy of CADC increases the output devices' over-drive voltage and decreases output loading. The proposed design methods allow closed-loop MDAC to operate at high speed while maintaining low power consumption. The measured SFDR, SNR, and SNDR are 40.7 dB, 33.8 dB, and 33.7 dB, respectively, at the Nyquist rate input. The ADC power dissipation is 49 mW and corresponds to a figure-of-merit (FoM) of 1.24 pJ/conv.-step. The active area occupies 0.16<formula formulatype="inline"><tex Notation="TeX">$~{\hbox {mm}}^{2}$</tex></formula>. </para>