An 800-MOPS, 110-mW, 1.5-V, parallel DSP for mobile multimedia processing

Abstract

This paper presents a newly developed parallel digital signal processor (DSP) for mobile multimedia processing. The DSP achieves 800 MOPS at 110 mW (1.5 V) through its task-parallel processing on four DSP cores. The parallel architecture, including data sharing and synchronization mechanisms, is carefully designed to be hardware and power efficient for portable multimedia applications. By using the parallel processing architecture, clock gating, and other low-power methods, about 85% power reduction is achieved. The 9.2-mm-square die contains 5.2-M transistors with 0.25-/spl mu/m CMOS process.