2006 · 28 citations · 1 references
EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignDevice ScalingEtching ProcessesIntegrated Circuit DesignStrain EngineeringVery-large-scale Integration LayoutBoundary EffectsElectromigration-aware LayoutGeometry EffectsHigh PerformanceLayout-dependent EffectsOscillator CircuitsOscillator DevicesThree-dimensional Integrated Circuit Layout
We report, for the first time, on the 2D boundary effects in a high performance 65nm SOI technology with dual etch stop layer (dESL) stressors. 1D geometry effects, such as poly pitch dependence, and the implications on SPICE models and circuit design are also discussed. It will be shown that PMOS and ring oscillator performance can be significantly enhanced by optimizing the transverse and lateral placement of the dESL boundary
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Piezoresistance Effect in Germanium and Silicon
Charles S. Smith · Physical Review · 1954 · 2K citations