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A 40 MFLOPS digital signal processor: The first supercomputer on a chip
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2005
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EngineeringComputer ArchitectureSystem-level DesignProcessor ArchitectureTexas InstrumentsHardware ArchitectureInternal ParallelismHardware SecurityHigh-performance ArchitectureSystems EngineeringParallel ComputingManycore ProcessorThird Generation MemberComputer EngineeringComputer ScienceMicroelectronicsSignal ProcessingFirst SupercomputerSystem On ChipCo-processorsHardware AccelerationSystem Software
The TMS320C30 is Texas Instruments' third generation member of a family of compatible Digital Signal Processors. With a computational rate of 40 MFLOPS (Million Floating-Point Operations per Second), the TMS320C30 far exceeds the performance of any programmable DSP available today. Total system peformance has been maximized through internal parallelism, more than twenty four thousand bytes of on-chip memory, single-cycle floating-point operations, and concurrent I/O. The total system cost is minimized with on-chip memory and on-chip peripherals such as timers and serial ports. Finally, the user's system design-time is dramatically reduced with the availability of the floating-point operations, general purpose instructions and features, and quality development tools.