A 14bit Digitally Self-Calibrated Pipelined ADC with Adaptive Bias Optimization for Arbitrary Speeds up to 40MS/s

Abstract

A 14bit digitally self-calibrated pipelined ADC featuring the adaptive bias optimization is fabricated in a 0.18/spl mu/m dual-gate CMOS and consumes 19.2, 33.7, 50.5 and 72.8mW respectively when operating at 10, 20, 30 and 40MS/s. In all the operating speeds with temperature variation up to 80/spl deg/C, DNL is kept between /spl plusmn/0.60LSB. When operating at 20MS/s, it achieves 73.2dB SNR and 70.4dB SNDR.