A single-chip concatenated FEC decoder

Abstract

A single chip decoder, which implements the concatenated forward error correction functions for a digital satellite receiver system, has been designed. The functions include Viterbi decoding, convolutional deinterleaving, Reed-Solomon decoding, data stream synchronization and descrambling. The device has been fabricated in a 0.6 /spl mu/m CMOS cell-based technology and is fully functional at data rates of 73 Mbits/sec at 70/spl deg/C and 4.75 V.