IEEE Photonics Technology Letters · 2005 · 13 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsOptoelectronicsSemiconductor DevicesCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyIntegrated PhotonicsOptical Communication SystemsOptical InterconnectsPhotonic Integrated CircuitsChip-to-chip Optical InterconnectsComplementary Metal-oxide-semiconductor DesignComplementary Metal-oxide-semiconductor DevicesInterconnect Power DissipationOn-chip Optical InterconnectsOptical TransceiversTransceiver Design
A novel bidirectional complementary metal-oxide-semiconductor (CMOS) transceiver for chip-to-chip optical interconnects operating at 2.5 Gb/s is proposed, which shares the common block of a receiver and a transmitter on a single chip. The share of the common block of two circuits makes it possible to save 55% or 20% of power dissipation, depending on the operating mode. The chip in 0.18-μm CMOS technology occupies an area of 0.82×0.82 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , 70% of the total area of a typical unshared transceiver chip. The transmitting and receiving modes of operation show -3-dB bandwidths of 2.2 and 2.4 GHz and electrical isolations of -28 and -40 dB, respectively.
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