Algorithm and implementation of the K-best sphere decoding for MIMO detection

Zhan Guo, Peter Nilsson

IEEE Journal on Selected Areas in Communications · 2006 · 704 citations · 27 references

Concepts

TL;DR

The paper proposes a K‑best Schnorr‑Euchner (KSE) decoding algorithm and a modified KSE (MKSE) variant, along with a VLSI architecture, to achieve near‑maximum‑likelihood performance for MIMO detection. The hard‑output KSE and soft‑output MKSE decoders are implemented in 0.35‑μm and 0.13‑μm CMOS, respectively, for 4×4 16‑QAM MIMO detection. The implementations deliver near‑ML performance with high throughput—53.3 Mb/s for hard‑output and >100 Mb/s for soft‑output—while occupying 5.76 mm² (91 K gates) and 0.56 mm² (97 K gates) and consuming 626 mW, demonstrating low‑complexity, high‑throughput VLSI feasibility.

Abstract

K-best Schnorr-Euchner (KSE) decoding algorithm is proposed in this paper to approach near-maximum-likelihood (ML) performance for multiple-input-multiple-output (MIMO) detection. As a low complexity MIMO decoding algorithm, the KSE is shown to be suitable for very large scale integration (VLSI) implementations and be capable of supporting soft outputs. Modified KSE (MKSE) decoding algorithm is further proposed to improve the performance of the soft-output KSE with minor modifications. Moreover, a VLSI architecture is proposed for both algorithms. There are several low complexity and low-power features incorporated in the proposed algorithms and the VLSI architecture. The proposed hard-output KSE decoder and the soft-output MKSE decoder is implemented for 4/spl times/4 16-quadrature amplitude modulation (QAM) MIMO detection in a 0.35-/spl mu/m and a 0.13-/spl mu/m CMOS technology, respectively. The implemented hard-output KSE chip core is 5.76 mm/sup 2/ with 91 K gates. The KSE decoding throughput is up to 53.3 Mb/s with a core power consumption of 626 mW at 100 MHz clock frequency and 2.8 V supply. The implemented soft-output MKSE chip can achieve a decoding throughput of more than 100 Mb/s with a 0.56 mm/sup 2/ core area and 97 K gates. The implementation results show that it is feasible to achieve near-ML performance and high detection throughput for a 4/spl times/4 16-QAM MIMO system using the proposed algorithms and the VLSI architecture with reasonable complexity.

References

27