Design Optimization of a Type-I Heterojunction Tunneling Field-Effect Transistor (I-HTFET) for High Performance Logic Technology

Abstract

In this work, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated. TFETs based on either silicon or compound semiconductors have been intensively researched due to their merits of robustness against short channel effects (SCEs) and excellent subthreshold swing (SS) characteristics. However, silicon TFETs have the drawback of low on-current and compound ones are difficult to integrate with silicon CMOS circuits. In order to combine the high tunneling efficiency of narrow bandgap material TFETs and the high mobility of rn.v TFETs, a Type-I heterojunction tunneling field-effect transistor (I-HTFET) adopting Ge-AI<SUB>x</SUB>Ga<SUB>1-x</SUB>AsGe system has been optimized by simulation in terms of aluminum (AI) composition. To maximize device performance, we considered a nanowire structure, and it was shown that high performance (UP) logic technology can be achieved by the proposed device. The optimum AI composition turned out to be around 20% (x=0.2).