Electrical Characteristic Fluctuations in Sub-45nm CMOS Devices

Abstract

Random fluctuations of electrical characteristics in sub-45nm CMOS devices introduced by process-parameter variations through severe short channel effects have made the scaling of conventional planar transistors much more difficult than ever before, especially while further reduction of gate dielectric thickness is ambiguous. In this paper, the authors systematically investigate the fluctuations of threshold voltages at varied gate length, considering the effects of channel doping, gate dielectric thickness, and new transistor structures such as thin-buried-oxide SOI and FinFETs. Quantitative analysis is undertaken in terms of three major variation sources: random doping distribution, gate length deviation, and line edge roughness. The analysis also features a low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> -fluctuation transistor for 16nm node achieved with undoped body, mid-gap metal gate, and nanowire channel