2008 · 20 citations · 1 references
EngineeringComputer EngineeringComputer ScienceDigital CommunicationFault-tolerant ComputingFault-tolerant SystemsCoding TheoryError Control CodingError CorrectionError-correcting CodesFault-tolerant CommunicationRedundancy TechniquesBit Error RateBit-error Rate AnalysisCyclic CodesCyclic Redundancy ChecksError Correction CodesParity Check CodesRedundancy SchemesSoft Error Correction
The paper proposes a method that links judge and data checks to enable multiple‑bit error correction using cyclic redundancy check codes. The method’s error‑correction principle and detailed implementation, including key parameter design, are described. Simulations demonstrate that the method effectively reduces bit error rate and packet error rate.
A method which links the judge and data check is provided. The method realizes the ability of multiple bits error correction using cyclic redundancy check codes. The error correction principle and realization method are described in detail. The key parameters design of the method is analyzed. The simulation results show that the multiple bits error correction method can improve the bit error rate and packet error rate effectively.
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