PipeRench implementation of the instruction path coprocessor

Abstract

T his pape r de monstrates how an Ins truction Path Copr ocessor (I-COP) can be efficiently implemented using the P ipeRench reconfigurable architecture. An I-COP is a progr ammable on-chip coprocessor that operates on the core pr ocessor's instructions to tr ansform them into a new format t hat can be more efficiently executed. The I-COP can be us ed to implement many sophisticated hardware code modif ication techniques. We show how four specific techniques c an be map ped to t he P ipeRench pi pelined c omputation mode l. The experimental results show that a PipeRench I-COP used to perform trace construction and trace optimiz ations for a tr ace c ache fi ll unit not o nly ac hieves goo d pe rformance gai ns but can p otentially be impl emented i n le ss than 10 mm 2 (assuming 0.18 micron technology) or appr oximately 3% of the die area of a current high-end micropr ocessor. W e be lieve these r esults d emonstrate the us efulness and feasibility of the I-COP concept.