Partially Reversible Pipelined QCA Circuits: Combining Low Power With High Throughput

Abstract

This paper introduces an architecture for quantum-dot cellular automata circuits with the potential for high throughput and low power dissipation. The combination of regions with Bennett clocking and memory storage combines the low power advantage of reversible computing with the high throughput advantage of pipelining. Two case studies are initially presented to evaluate the proposed pipelined architecture in terms of throughput and power consumption due to information dissipation. A general model for assessing power consumption is also proposed. This paper shows that the advantages possible by using a Bennett clocking scheme also depend on circuit topology, thus also confirming the validity of the proposed analysis and model.