On-Chip processing for the wave union TDC implemented in FPGA

Abstract

The wave union TDC implemented in FPGA utilizes multiple measurement method to reach time resolution beyond the natural carry cell delay in FPGA. Lacking of analog compensation for bin width control available in ASIC, the wave union TDC takes the after-fact digital calibration approach. In addition to the temperature drift, non-uniformity of the carry chain structure in FPGA causes complicate differential non-linearity pattern which imposes significant on-chip calibration challenge. In this paper, processing strategies for the wave union TDC are discussed. Actual implementations in low-cost FPGA with 20 ps and 10 ps RMS resolutions are also presented.