Toward nanoelectronic cellular neural networks

Abstract

We investigate the use of nanoelectronic structures in cellular non-linear network (CNN) architectures, for potential application in future high-density and low-power CMOS-nanodevice hybrid circuits. We first investigate compact models for simulation of single-electron tunnelling (SET) transistors appropriate for use in coupled SET–CMOS circuits. We then discuss simple CNN linear architectures using a SET inverter topology as the basis for the non-linear transfer characteristic of individual cells. This basic SET CNN cell acts as a summing node, which is capacitively coupled to the inputs and outputs of nearest neighbour cells. Monte Carlo simulation results are then used to show CNN-like behaviour in attempting to realize different functionality such as a connected component detector and shadowing. Copyright © 2000 John Wiley & Sons, Ltd.