Simultaneous scheduling and allocation for cost constrained optimal architectural synthesis

Abstract

An integer programming (IP) model, which simultaneously schedules and allocates functional units, registers, and busses, is presented for synthesizing cost-constrained globally optimal architectures. This research is important for industry by providing optimal schedules which minimize interconnect costs and interface to analog and asynchronous processes, since these are seen as key to synthesizing high performance architectures. A partially structured tight IP formulation of the architectural synthesis problem provides globally optimal schedules for peicewise linear cost functions, using branch and bound, in execution times faster than previous research. This research breaks new ground by 1. simultaneously scheduling and allocating hardware resources including interconnect, 2. support for asynchronous and analog interfaces, and 3. guaranteeing globally optimal solutions in practical execution times.