A scaleable, radiation hardened shallow trench isolation

Abstract

Shallow trench isolation (STI) is rapidly replacing LOCOS (LOCal Oxidation of Silicon) as the device isolation process of choice. However, little work has been done to characterize the radiation-hardness capability of devices built with STI. In this paper, some of the basics of STI devices are examined, such as the radiation response of unhardened STI devices. We discuss several issues affecting the total dose hardness of unhardened STI. These issues have critical implications for the hardness of CMOS built using STI in commercial foundries. Finally, data from hardened STI devices are presented. Total dose hardened STI devices are demonstrated on devices with gate widths down to 0.5 /spl mu/m.